The invention relates to electronic semiconductor devices, and, more particularly, to transistor structures and fabrication methods for such structures.
The performance of high density integrated circuits depends upon transistor performance, but the scaling down of transistor dimensions makes it difficult to maintain low sheet resistance and low junction leakage for conventional titanium or cobalt self-aligned silicide processes. One of the major problems is that the sheet resistance of very narrow gates has a large range in resistance, which can have a significant impact on circuit performance. The large range in resistance is due to the difficulty in controlling the width of the narrow gates and controlling the self-aligned silicide on these narrow gates. A second problem is the gate silcide shorting to the source/drain silicide over the sidewall spacer as a result of incomplete removal of the metal on the sidewall spacer. An additional problem is that adjacent transistor gates can become shorted because the gate electrode silicide overgrowth may bridge to the next transistor gate. Another major problem is that the source/drain silicidation process can short through the shallow source/drain junctions of very short channel transistors.
Nakahara et al, "Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS", 1996 Symp VLSI Tech Dig 174-175 improves transistor performance by use of a raised source/drain structure.